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          如何搭建适用于自己电脑vivado版本的lab
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        <p>此文档并不会给的特别详细，一些特别基础的部分比如怎么去创建一个新的工程这里是不会一步步截图的，这里只是给大家看一个总体的流程，毕竟每个人电脑vivado版本不一样，贴图的vivado版本是2018.3。</p>
<a id="more"></a>

<ol>
<li><p>新建一个vivado工程，放在哪里看自己喜欢，工程怎么命名也看自己喜欢，路径不要有中文就行（当然有也可以，只不过有些情况下综合会报错，到时候重新按流程走一遍就行）</p>
<p> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/1.png" alt="1"></p>
</li>
<li><p>板子型号选择xc7a100tcsg324-1</p>
<p> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/2.png" alt="2"></p>
</li>
<li><p>创建好工程后将下图的文件夹从lab1拷过来</p>
<p><img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/3.png" alt="3"></p>
</li>
<li><p>回到vivado，点击左边栏的Create Block Design，命名自己看着办就行，只要后面自己能对的上</p>
<p> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/4.png" alt="4"></p>
</li>
<li><p>添加IP核，实验中所有的IP核除了MIPS_MicroAptiv_UP是自己封装的之外都可以直接在Diagram界面输入名字找到，IP核的名字在每个模块的正下方，上方是它实例化时的名字</p>
<p> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/5.png" alt="5"></p>
<p> 1）首先我们将自己封装的MIPS_MicroAptiv_UP导入，点击左边栏最上面的settings，选择IP-&gt;Repositoty添加我们之前复制过来的ip_repo的路径，这样就导入了MIPS_MicroAptiv_UP的IP，实验一给的是自己已经封装好的IP，这是一个具有完整功能的MIPS CPU，感兴趣的同学可以自己试着去自己封装下，当然不建议（我自己能封装好我肯定会让你们自己搭的怎么会直接用以前的）<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/6.png" alt="6"><br> 点击OK，Apply，OK然后在Diagram界面点击加号输入名字把IP添加进来<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/7.png" alt="7"><br> 2）然后就可以去添加其他模块了，建议把实验一的block design打开一个个对着添加IP，添加好之后点击一下这个IP对比实验一的IP进行配置<br> 注意两点：<br> AXI BRAM Controller的Memory Depth 和ID Width是根据它连接的Slave自动配置的，我们不用管。<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/8.png" alt="8"><br> Blk_mem_gen_0 加载初始化文件位置是我们刚刚复制过来的位置<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/9.png" alt="9"><br> 3）将所有的IP连线，暂时先不管那些引脚<br> 注意：<br> 有些接口是需要点击+号才能出来的<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/10.png" alt="10"><br> 所有连线连接完毕后是这个样子<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/11.png" alt="11"><br> 4）添加引脚，以Clocking Wizard的clk_in1为例，我们点击这个端口然后右键选择Make External<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/12.png" alt="12"><br> 然后点击生成的引脚，在External Port Properties这个小界面修改它的名字为CLK100MHZ，这是为了和约束文件的引脚相对应，这样我们就不用该约束文件了，当然你也可以不改这个名字去约束文件里把对应CLK100MHZ的名字改了<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/13.png" alt="13"><br> 其他的引脚操作类似。<br> 注意：<br> 引脚是区分大小写的，所以该大写的还是要大写<br> 一些引脚修改名字后Diagram上显示会有[0:0]，这个并没有问题，习惯就好<br> 最后所有引脚添加完毕后整个block design是这样的<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/14.png" alt="14"><br> 5）地址映射，点击Diagram右边的Address Editor进行地址分配（如果没有那就是你关掉了，在Window-&gt;Address Editor重新打开<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/15.png" alt="15"><br> 先点击自动分配地址的按钮，然后把地址修改成如图所示<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/16.png" alt="16"></p>
</li>
<li><p>在Source界面右键选择Create HDL Wrapper生成顶层文件<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/17.png" alt="17"><br> 选项的话，选哪个都行，建议选第二个让vivado自动更新就好<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/18.png" alt="18"><br> 这里会出两个Warning，由于时间问题以及对后面的实验没有影响就没有去消，有强迫症的话可以去搜搜到底是什么原因然后把warning消了，消完记得把方法写在该文档上造福后人嗷<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/19.png" alt="19"></p>
</li>
<li><p>点击左边栏的Generate Block Design，对Block Design进行综合，Run Setting线程数开到最大，这样会更快</p>
<p> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/20.png" alt="20"></p>
</li>
<li><p>添加约束文件，将之前复制过来的约束文件添加进来。或者自己创建一个.xdc文件，然后把实验一MIPSfpga.xdc的内容复制来，大家可以看一看block design中的那些引脚都绑定到板子的什么位置去了。</p>
</li>
<li><p>生成比特流文件，注意，这里可能会因为前面的[0:0]出一点小问题，由于vivado版本不同有些人可能没有[0:0]所以在这里专门说一下，生成比特流的时候会报错：<br> <img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/21.png" alt="21"><br> 你仔细看的话会发现已经把怎么改告诉我们了，在约束文件中找到对应的行把set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JB4_IBUF] 改成set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {JB4_IBUF[0]}]就可以了，然后点击Generate Bistream生成比特流文件，线程数还是开到最大。</p>
</li>
<li><p>到此一个适用于自己电脑版本的lab1就已经生成完毕了，大家可以将生成的比特文件烧录到板子上，然后按CPU RESET按钮，可以看到LED灯全亮，其中LED14 和LED 15是常闪，将软件程序通过JTag烧录到板子上后可以看到跑马灯。</p>
</li>
<li><p>向自己动手做的同学在之后的实验可以直接复制不同实验的_C文件夹到当前文件夹然后试着自己添加IP，引脚什么的，像这样</p>
<p><img src="/HUST_cs_jiekou/2021/02/14/%E5%A6%82%E4%BD%95%E6%90%AD%E5%BB%BA%E9%80%82%E7%94%A8%E4%BA%8E%E8%87%AA%E5%B7%B1%E7%94%B5%E8%84%91vivado%E7%89%88%E6%9C%AC%E7%9A%84lab/22.png" alt="22"></p>
</li>
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